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Method of fabricating a memory device having a memory array including a plurality of memory cell transistors arranged in rows and columns
Method of fabricating a memory device having a memory array including a plurality of memory cell transistors arranged in rows and columns
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机译:具有具有包括以行和列布置的多个存储单元晶体管的存储阵列的存储装置的制造方法
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摘要
A method of fabricating a memory device in a semiconductor substrate, the device having a memory array having a plurality of memory cell transistors arranged in rows and columns. The method includes forming a plurality of tunneling field effect transistors, forming a first well of the second doping type, forming a second well of the first doping type surrounding the first well, forming a first word line connected to a first row of memory cell transistors, forming a first bit line to control a voltage of doped drain regions of tunneling field effect transistors of a first column of memory cell transistors, and forming a second bit line parallel to the first bit line.
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