IMPROVED STRUCTURE FOR CMOS ETSOI WITH MULTIPLE THRESHOLD VOLTAGES AND ACTIVE WELL BIAS CAPABILITY

摘要

A structure includes a semiconductor substrate (1) having a first conductivity type; an insulating layer (2) disposed over the top surface; a thin semiconductor layer (3) disposed over the insulating layer (2) and a plurality of transistor devices (10a-b) disposed upon the semiconductor layer (3). Isolation regions (6) are formed between adjacent transistor devices extending through the semiconductor layer (3) to a depth sufficient for electrically isolating the adjacent transistor devices from one another. Additional isolation regions (7a-d) are formed between selected adjacent transistor devices extending through the silicon layer (3) and insulating layer (2) into the substrate (1), such that electrically isolated first and second well regions (4a-d) are formed. Back gate regions (contacts) (9a-c), of the first conductivity type, are disposed wholly within a well region (4) underlying one of the transistor devices (10) and are electrically floating within the well region (4). During operation, back gate regions (9a-c) may be individually biased by leakage and capacitive coupling using a bias potential applied to the well regions (4a-d).