WIRING RESISTANCE EXTRACTION DEVICE, WIRING RESISTANCE EXTRACTION METHOD, WIRING RESISTANCE EXTRACTION PROGRAM, AND COMPUTER-READABLE RECORDING MEDIUM

摘要

PROBLEM TO BE SOLVED: To estimate in real time a wiring resistance between arbitrary two points in a layout pattern in the layout design of a semiconductor device, thereby preventing as much as possible a rework in a final design check, or a redesign, from being required and so allowing a design period to be shortened.;SOLUTION: A wiring resistance extraction device 100, which extracts a combined resistance between arbitrary two points on wiring on the basis of layout information of a semiconductor integrated circuit, includes: a figure processing unit 110a that extracts a plurality of rectangular figures, which indicate the wiring on a current path from a first point to second point, on the basis of positional information that specifies the first point and second point on the wiring, and that creates a final rectangular figure which has the same length as a sum total of the lengths of the plurality of rectangular figures and is equivalent to the plurality of rectangular figures with respect to a wiring resistance; and a resistance calculation unit 110b that calculates the combined resistance between the two points on the wiring on the basis of the ratio of the width to length of the final rectangular figure.;COPYRIGHT: (C)2014,JPO&INPIT