CIRCUIT HAVING PROGRAMMABLE COINCIDENCE DETERMINATION FUNCTION, LUT CIRCUIT HAVING THE SAME, MUX CIRCUIT HAVING THE SAME, FPGA DEVICE HAVING THE SAME AND DATA WRITING METHOD

摘要

PROBLEM TO BE SOLVED: To improve an occupancy area or a circuit delay.;SOLUTION: A circuit according to an embodiment includes: a bit string comparator having a match line to which coincidence determination terminals of two or more one bit comparators are connected; pair wiring including two or more search lines and inverted search lines; a common match line, one pre-charge transistor, and an output invertor. The one bit comparator includes: at least first and second input terminals; first and second coincidence determination terminals; and a memory for storing a pair of data and inverted data. The first input terminal of the one bit comparator is connected to the search line, the second input terminal of the one bit comparator is connected to the inverted search line, the match line of the bit string comparator is connected to the common match line, the source of the pre-charge transistor is connected to a supply voltage line, the drain of the pre-charge transistor is connected to the common match line, and the common match line is connected to the input of the output invertor.;COPYRIGHT: (C)2014,JPO&INPIT