A conversion circuit includes: a conversion section configured to convert each of analog pixel signals into digital pixel data; a timing acquisition section configured to acquire specified timing, in which the specified timing defines a display period during which display of each of the analog pixel signals is performed in a cycle of a synchronization signal; a timing setting section configured to set timing that defines an extension period that is longer than the display period, in which the timing is other than the specified timing; an enable signal generation section configured to generate an enable signal, in which the enable signal indicates the extension period as a period during which the digital pixel data is valid; and an output section configured to output the digital pixel data that is valid, in accordance with the enable signal.
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