Noise Temperature Extraction Procedure for Characterization of On-Wafer Devices

摘要

A procedure for obtaining noise temperatures of a field effect transistor (FET) embedded on a wafer through an analytical procedure which processes measured noise figure data over transistor's size P_d within a frequency range at constant voltage and current density. The parasitic elements associated with an electrical model of the embedding structures are determined. Then, for each of n=1, 2, . . . N FETs, the scattering parameters and noise figure F_meas,n are measured, the components of the core model, normalized to the periphery P_d are determined, and the noise contributions of the parasitic components are de-embedded from F_meas,n. The noise temperatures t_gs, t_ds, and t_gd are found by solving the equation; $$ \frac{4N_iG_s\left(F_{\mathrm{meas},n}-1\right)-y_s^{+}C_{T_A}y_s-y_s^{+}T_{B,n}T_AC_{T_C}T_A^{+}T_{B,n}^{+}y_s}{P_{d_n}}=A_nt_{\mathrm{ds}}+B_nt_{\mathrm{gs}}+C_nt_{\mathrm{gd}}$$ ;using at least three values of F_meas,n and P_d,n. Finally, the noise temperatures T_gs, T_ds, and T_gd are found, where T_gs=t_gs*T₀, T₀=290K; T_ds=t_ds*T₀; and T_gd=t_gd*T₀.