首页> 外国专利> GATED CIRCUIT STRUCTURE WITH ULTRA-THIN, EPITAXIALLY-GROWN TUNNEL AND CHANNEL LAYER

GATED CIRCUIT STRUCTURE WITH ULTRA-THIN, EPITAXIALLY-GROWN TUNNEL AND CHANNEL LAYER

机译:超薄,表观生长的隧道和通道层的门控电路结构

摘要

A semiconductor device and tunnel field-effect transistor, and methods of fabrication thereof are provided. The device includes first and second semiconductor regions, an intermediate region, and an epitaxial layer. The intermediate region separates the first and second semiconductor regions, and the epitaxial layer extends at least partially between the first and second regions over or alongside of the intermediate region. A gate electrode is provided for gating the circuit structure. The epitaxial layer is disposed to reside between the gate electrode and at least one of the first semiconductor region, the second semiconductor region, or the intermediate region. The epitaxial layer includes an epitaxially-grown, ultra-thin body layer of semiconductor material with a thickness less than or equal to 15 nanometers. Where the semiconductor device is a tunneling field-effect transistor, the intermediate region may be a large band-gap semiconductor region, with a band-gap greater than that of the epitaxial layer.
机译:提供一种半导体器件和隧道场效应晶体管及其制造方法。该器件包括第一和第二半导体区域,中间区域和外延层。中间区域将第一半导体区域和第二半导体区域分开,并且外延层在中间区域上方或旁边至少部分地在第一区域和第二区域之间延伸。提供栅电极用于选通电路结构。外延层设置为位于栅电极与第一半导体区域,第二半导体区域或中间区域中的至少一个之间。外延层包括半导体材料的外延生长的超薄主体层,其厚度小于或等于15纳米。在半导体器件是隧穿场效应晶体管的情况下,中间区域可以是带隙大于外延层的带隙的大带隙半导体区域。

著录项

  • 公开/公告号US2014054549A1

    专利类型

  • 公开/公告日2014-02-27

    原文格式PDF

  • 申请/专利权人 WEI-YIP LOH;WEI-E WANG;

    申请/专利号US201213592805

  • 发明设计人 WEI-YIP LOH;WEI-E WANG;

    申请日2012-08-23

  • 分类号H01L29/775;H01L21/20;

  • 国家 US

  • 入库时间 2022-08-21 16:05:22

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