首页> 外国专利> Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate

Semiconductor device and method of forming high routing density BOL BONL and BONP interconnect sites on substrate

机译:半导体器件和在衬底上形成高布线密度的BOL BONL和BONP互连位点的方法

摘要

A semiconductor device has a semiconductor die with a plurality of bumps formed over contact pads on a surface of the semiconductor die. The bumps can have a fusible portion and non-fusible portion. A plurality of conductive traces is formed over a substrate with interconnect sites having a width greater than 20% and less than 80% of a width of a contact interface between the bumps and contact pads. The bumps are bonded to the interconnect sites so that the bumps cover a top surface and side surface of the interconnect sites. An encapsulant is deposited around the bumps between the semiconductor die and substrate. The conductive traces have a pitch as determined by minimum spacing between adjacent conductive traces that can be placed on the substrate and the width of the interconnect site provides a routing density equal to the pitch of the conductive traces.
机译:半导体器件具有半导体管芯,该半导体管芯具有在半导体管芯的表面上的接触焊盘上方形成的多个凸块。凸块可具有可熔部分和非可熔部分。多个导电迹线形成在具有互连部位的衬底上,该互连部位的宽度大于凸块和接触垫之间的接触界面的宽度的20%且小于80%。凸块结合到互连部位,使得凸块覆盖互连部位的顶表面和侧面。密封剂沉积在半导体管芯和衬底之间的凸块周围。导电迹线具有由可放置在基板上的相邻导电迹线之间的最小间隔确定的间距,并且互连部位的宽度提供了等于导电迹线的间距的布线密度。

著录项

  • 公开/公告号US8841779B2

    专利类型

  • 公开/公告日2014-09-23

    原文格式PDF

  • 申请/专利权人 RAJENDRA D. PENDSE;

    申请/专利号US20100961027

  • 发明设计人 RAJENDRA D. PENDSE;

    申请日2010-12-06

  • 分类号H01L21;H01L23/48;H01L21/56;H01L23/498;H05K1/11;H01L23;H01L25/065;H05K3/34;

  • 国家 US

  • 入库时间 2022-08-21 16:04:14

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