Circuit and method for finding the sampling phase and canceling intersymbol interference in a decision feedback equalized receiver

摘要

A circuit comprises an analog to digital converter (ADC) that samples a received signal based on a sampling clock. A feed forward filter communicates with the ADC and does not remove first precursor intersymbol interference from the received signal. An adaptive timing loop circuit that adjusts a timing phase of the sampling clock of said ADC to remove the first precursor intersymbol interference from the received signal. The adaptive timing loop circuit adjusts the timing phase based on at least one of an estimate signal and a loop gain control constant.