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Synthesis of area-efficient subtractor and divider functional blocks
Synthesis of area-efficient subtractor and divider functional blocks
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机译:面积有效的减法器和除法器功能块的综合
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摘要
In one embodiment of the invention, a method of designing an integrated circuit including a subtraction arithmetic function is provided. The method includes generating a netlist of an area-efficient subtractor to subtract a first input vector from a second input vector. A netlist of a plurality of reduced full subtractor cells is generated with each including an exclusive-NOR gate evaluating a shared Boolean expression to generate a sum bit output and a carry bit output. The netlist of the reduced full subtractor cell is replicated for all bits of the area-efficient subtractor but for the least significant bit. One of a plurality of netlists of subtractor cells is selected for the least significant bit of the area-efficient subtractor in response to a flex bit.
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