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Multi-level integrated circuit, device and method for modeling multi-level integrated circuits

机译:多级集成电路,用于对多级集成电路建模的设备和方法

摘要

A multi-level integrated circuit, having a superposition of a first stack and a second stack of layers, and including a first row of electronic devices produced in the first stack, extending parallel to a first direction and fitting into a first volume with a substantially parallelepiped rectangle shape and having edges perpendicular to the first direction and with dimension H1; a second row of electronic devices produced in the second stack, extending parallel to the first direction and fitting into a second volume with a substantially parallelepiped rectangle shape and having edges perpendicular to the first direction and with dimension H2H1; and a plurality of electrical connection elements passing through the second stack of layers, each connection element fitting into a third volume arranged on the first volume and next to the second volume.
机译:一种多层集成电路,具有第一叠层和第二叠层的叠置,并且包括在第一叠层中生产的第一行电子设备,第一行电子设备平行于第一方向延伸,并以基本上平行六面体矩形,边缘垂直于第一方向,尺寸为H 1 ;在第二堆叠中生产的第二行电子设备,其平行于第一方向延伸并装配到具有大致平行六面体矩形形状且边缘垂直于第一方向且尺寸为H 2 的第二体积中 1 ;多个电连接元件穿过第二层堆叠,每个电连接元件装配到布置在第一体积上并且紧挨第二体积的第三体积中。

著录项

  • 公开/公告号US8710671B2

    专利类型

  • 公开/公告日2014-04-29

    原文格式PDF

  • 申请/专利权人 SHASHIKANTH BOBBA;OLIVIER THOMAS;

    申请/专利号US201113335213

  • 发明设计人 SHASHIKANTH BOBBA;OLIVIER THOMAS;

    申请日2011-12-22

  • 分类号H01L23/48;H01L23/538;

  • 国家 US

  • 入库时间 2022-08-21 16:00:23

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