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Digital logic circuit with dynamic logic gate
Digital logic circuit with dynamic logic gate
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机译:具有动态逻辑门的数字逻辑电路
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摘要
A digital logic gate suitable for a high-speed operation of a central processing unit. The digital logic gate comprises the first dynamic logic gate configured to logically gate a plurality of first input data in response to the first clock signal, a second dynamic logic gate configured to logically gate a gating output of the first dynamic logic gate and a plurality of second input data, and a latching device configured to latch a gating output of the second dynamic logic gate. The digital logic circuit need not adopt a keeper circuit, and thus a gate delay is reduced and the digital logic circuit performs a high-speed gating operation with robust characteristic against a current leakage or an input noise.
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