Digital logic circuit with dynamic logic gate

摘要

A digital logic circuit suitable for high-speed computation of a central processing unit is disclosed. Such a digital logic circuit includes a first dynamic logic gate that logically gates a plurality of first input data in response to a first clock signal. The first dynamic logic gate does not employ a keeper circuit. The digital logic circuit further includes a second dynamic logic gate for logically gating the gating output of the first dynamic logic gate and the plurality of second input data in response to the pulse signals and a second dynamic logic gate for providing a gating output of the second dynamic logic gate Latching device for latching. The digital logic circuit according to the embodiment of the present invention does not employ a keeper circuit in the dynamic logic gate, so that the gate delay is reduced. In addition, the digital logic circuit has a characteristic that is relatively strong against leakage or input noise while performing a fast gating operation.