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Sub-pixel generation for high speed color laser printers using a clamping technique for PLL (phase locked loop) circuitry
Sub-pixel generation for high speed color laser printers using a clamping technique for PLL (phase locked loop) circuitry
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机译:使用用于PLL(锁相环)电路的钳位技术为高速彩色激光打印机生成亚像素
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摘要
Methods and apparatus for optimizing the phase lock loop circuitry of sub-pixel clock generators for situations where frequent switching between different system printing speeds, and hence clock frequencies are required. An optimizing circuit is associated with a sub-pixel clock generator for clamping an input voltage to a voltage controlled oscillator controlling clock frequency between a desired range. The clamping circuitry comprises a comparator for detecting when the voltage has moved out of the desired range and then charges or discharges a loop filter circuit controlling the input voltage to the VCO to keep the input voltage within the desired range.
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