An equalized-impedance shadowed current cell can be arrayed in a Digital-to-Analog Converter (DAC) or other converters or applications. The Equalized-impedance shadowed current cell has primary differential transistors in parallel with shadow differential transistors that have gates driven inversely to gates of the primary differential transistors. A shadow current from the shadow differential transistors is much smaller than a primary current switched by the primary differential transistors. Cell current is not switched off to zero but to the shadow current. The ON state and OFF state impedances of the current cell may be matched during circuit design so that the impedance is the same regardless of digital input values. The Width and Length of the shadow differential transistors are adjusted so that overall output impedances for the ON and OFF states of the current cell are matched. Since output impedance is input code independent, high-speed performance is improved.
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