首页> 外国专利> METHODS OF FORMING LAYERS OF SEMICONDUCTOR MATERIAL HAVING REDUCED LATTICE STRAIN, SEMICONDUCTOR STRUCTURES, DEVICES AND ENGINEERED SUBSTRATES INCLUDING SAME

METHODS OF FORMING LAYERS OF SEMICONDUCTOR MATERIAL HAVING REDUCED LATTICE STRAIN, SEMICONDUCTOR STRUCTURES, DEVICES AND ENGINEERED SUBSTRATES INCLUDING SAME

机译:具有减少的晶格应变,半导体结构,器件和工程化的基体(包括相同的结构)的半导体材料形成层的方法

摘要

steps of a method for fabricating semiconductor devices or structures forming the flexible material layer overlying the semiconductor material structure and then a step of utilizing a semiconductor material comprising changing the viscosity of the dielectric material so as to relax the structure , and subsequent relaxation the relaxed semiconductor material layer to form a semiconductor structure with a seed layer material . In some embodiments, the semiconductor material layer may include, for example, a III-V semiconductor material such as indium gallium nitride . New intermediate structure are formed in this way in the middle . Processed substrates are semiconductor material comprises a continuous layer having a relaxed lattice structure . ;
机译:步骤,一种制造半导体器件或结构的方法,该方法形成覆盖半导体材料结构的柔性材料层,然后是利用半导体材料的步骤,包括改变介电材料的粘度以使结构松弛,随后使松弛的半导体松弛材料层与种子层材料形成半导体结构。在一些实施例中,半导体材料层可以包括例如III-V族半导体材料,诸如氮化铟镓。以这种方式在中间形成了新的中间结构。加工过的衬底是半导体材料,包括具有松弛晶格结构的连续层。 ;

著录项

  • 公开/公告号KR101408475B1

    专利类型

  • 公开/公告日2014-06-19

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20117009717

  • 发明设计人 아레나 챈탈;

    申请日2009-10-08

  • 分类号H01L21/786;H01L21/20;

  • 国家 KR

  • 入库时间 2022-08-21 15:40:44

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