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Iii - v - semiconductor structures with reduced pit - defective and a method of forming thereof

机译:减少凹坑缺陷的III-V族半导体结构及其形成方法

摘要

Embodiments relate to semiconductor structures and a method of forming thereof. In some embodiments the method can be used, semiconductor structures from iii - v - materials, such as, for example, ingan, to produce. It is an in - iii - v - semiconductor layer with a concentration of indium increase by means of a saturation region, in that the growth conditions, such as, for example, a temperature of a growth surface, are set in order to produce by means of saturation region, in which the in - iii - v - semiconductor layer with a reduced density of v - pits relative to the saturation region increases.
机译:实施例涉及半导体结构及其形成方法。在一些实施例中,可以使用由iii-v-材料(例如,铟)制成的半导体结构来制造该方法。它是一种铟-iii-v-半导体层,其铟浓度通过饱和区而增加,其方式是通过设置生长条件(例如生长表面的温度)来产生饱和区的一种方法,其中相对于饱和区而言,具有减小的v-pit密度的in-iii-v-半导体层会增加。

著录项

  • 公开/公告号DE112012000868T5

    专利类型

  • 公开/公告日2013-12-24

    原文格式PDF

  • 申请/专利权人 SOITEC;

    申请/专利号DE20121100868T

  • 申请日2012-02-17

  • 分类号C30B25/18;C30B29/40;C30B29/38;

  • 国家 DE

  • 入库时间 2022-08-21 15:37:36

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