Vertically stacked power FETs and synchronous buck converters with low on-resistance

摘要

The power FET (100) includes a lead frame including a pad (110), a first lead (111), and a second lead (112), a plate (150a), an extension (150b), and a ridge (150c). A first metal clip, vertically assembled in a space between the plate and pad, and a first n-channel FET chip (120) and a second n-channel FET chip (130) spaced from the plate and the extension and ridge connected to the pad Contains a stack containing The first FET chip has a source and gate terminal on the opposite surface to a drain terminal on one surface, the drain terminal is attached to the pad, and the source terminal is attached to the second clip (140) connected to the first lead. It is done. The second FET chip has a drain and gate terminal on the surface opposite to the source terminal on one surface, with the source terminal attached to the second clip and the drain terminal attached to the first clip. The drain-source on resistance of the FET stack is smaller than the on resistance of the first FET chip and the second FET chip.