digital phase detector of the digital integrator of a small area in the low-power

摘要

In an exemplary embodiment, the first phase locked loop circuit for receiving a reference signal and a source signal it may include a circuit. The first circuit can generate a correction signal indicating the phase difference between the reference signal and the source signal. Phase-locked loop may comprise a second circuit for receiving the correction signal. The second circuit may generate a digital signal indicating the phase to digital conversion of the correction signal. Phase-locked loop may include a third circuit for receiving a digital signal. The third circuit may generate a control signal indicating the converted voltage of the digital signal. Phase-locked loop may comprise a fourth circuit for receiving a control signal. The fourth circuit may generate a source signal in response to a control signal.