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LOW POWER AND COMPACT AREA DIGITAL INTEGRATOR FOR A DIGITAL PHASE DETECTOR
LOW POWER AND COMPACT AREA DIGITAL INTEGRATOR FOR A DIGITAL PHASE DETECTOR
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机译:用于数字相位检测器的低功耗和紧凑型数字积分器
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摘要
In an example embodiment, a phase-locked loop circuit may include a first circuitry to receive a reference signal and a source signal. The first circuitry may generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal. The phase-locked loop may include a second circuitry to receive the correction signal. The second circuitry may generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal. The phase-locked loop may include a third circuitry to receive the digital signal. The third circuitry may generate a control signal for demonstrating a converted voltage of the digital signal. The phase-locked loop may include a fourth circuitry to receive the control signal. The fourth circuitry may generate the source signal in response to the control signal.
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