TICC paradigm for building a formal validated parallel software for multi-core chips

摘要

The present invention teaches how to implement a massively parallel program that has been verified officially run effectively in shared memory multi-core chip and variance is (run). It allows a progressive refinement of the final implementation of their development programs from abstract statement of initial mutual behavior of the parallel between software components called cells. At each stage of refinement, a formal description of the pattern of events in the calculations are automatically derived from the implementation. This formal description is used for two purposes. The first one is to prove that there is no such as correctness, timing, progress, exclusion, deadlock / live rock. In order to report to identify patterns of important behavior and error, performance, pending, and the second self-monitoring system that constantly monitors in parallel applications without interfering with the timing in each application automatically (SMS It is to incorporate). The present invention also teaches how to minimize memory interference, you can protect your data, to increase the execution efficiency, configure shared memory multi-processor. None [Selection Figure]