Duty cycle correction circuit for the memory interface of the integrated circuit

摘要

The integrated circuit (the circuit and manner in order amendment the deformation of duty cycle of IC) inside are disclosed. IC, in order to receive the clock pulse, includes the supuritsuta circuit which is concatenated. The clock pulse is split into the clock pulse where two differs. One among the clock pulses is the version where another side reverses. The delay circuit is concatenated to each of the clock pulse. Each of the delay circuit generates the version which the clock pulse which corresponds delays. The amendment vessel circuit is concatenated in order to receive the both of the version which the clock pulse delays. The amendment vessel circuit generates the clock output signal which possesses the duty cycle amendment.