首页> 外国专利> INCREASE OF EPITAXY RESISTIVITY AND DECREASE OF JUNCTION CAPACITANCE BY ADDITION OF PBURIED LAYER

INCREASE OF EPITAXY RESISTIVITY AND DECREASE OF JUNCTION CAPACITANCE BY ADDITION OF PBURIED LAYER

机译:通过添加渗透层增加表观电阻率和减小结电容

摘要

An overvoltage protection device including: a doped substrate of a first conductivity type having a first doping level, coated with a doped epitaxial layer of the second conductivity type having a second doping level; a first doped buried region of the second conductivity type having a third doping level greater than the second level, located at the interface between the substrate and the epitaxial layer in a first portion of the device; and a second doped buried region of the first conductivity type having a fourth doping level greater than the first level, located at the interface between the substrate and the epitaxial layer in a second portion of the device.
机译:一种过电压保护装置,包括:具有第一掺杂水平的第一导电类型的掺杂衬底,其涂覆有具有第二掺杂水平的第二导电类型的掺杂外延层;第二导电类型的第一掺杂掩埋区,具有大于第二能级的第三掺杂能级,位于器件的第一部分中的衬底和外延层之间的界面处;第一导电类型的第二掺杂掩埋区具有大于第一能级的第四掺杂能级,位于器件的第二部分中的衬底和外延层之间的界面处。

著录项

  • 公开/公告号US2015221628A1

    专利类型

  • 公开/公告日2015-08-06

    原文格式PDF

  • 申请/专利权人 STMICROELECTRONICS (TOURS) SAS;

    申请/专利号US201414171931

  • 发明设计人 AURELIE ARNAUD;

    申请日2014-02-04

  • 分类号H01L27/02;H01L27/08;

  • 国家 US

  • 入库时间 2022-08-21 15:22:07

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