A successive approximation register analog-to-digital converter (SAR ADC) for high-speed applications. The SAR ADC uses at least one set of capacitors. Each set of capacitors is formed by 2M capacitor cells. The set of 2M capacitor cells is allocated into p capacitors C(p−1) to C0 decreasing in capacitance. C(p−1)C(p−2)+C(p−3)+ . . . +C0, and C(p−1) includes (2M-1−2q) capacitor cells.
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机译：适用于高速应用的逐次逼近寄存器模数转换器（SAR ADC）。 SAR ADC使用至少一组电容器。每组电容器由2 M 个电容器单元组成。将这组2个 M 个电容器单元分配到电容减小的p个电容器C（p-1）至C 0 中。 C（p-1） 0 ，并且C（p-1）包括（2 M-1 -2 q ）个电容器单元。
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