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Early cache eviction in a multi-flow network processor architecture

机译:多流网络处理器体系结构中的早期缓存逐出

摘要

Described embodiments provide an input/output interface of a network processor that generates a request to store received packets to a system cache. If an entry associated with the received packet does not exist in the system cache, the system cache determines whether a backpressure indicator of the system cache is set. If the backpressure indicator is set, the received packet is written to the shared memory. If the backpressure indicator is not set, the system cache determines whether to evict data from the system cache in order to store the received packet. If an eviction rate of the system cache has reached a threshold, the system cache sets a backpressure indicator and writes the received packet to the shared memory. If the eviction rate has not reached the threshold, the system cache determines an available entry and writes the received packet to the available entry in the system cache.
机译:所描述的实施例提供了网络处理器的输入/输出接口,该接口生成生成将接收到的分组存储到系统高速缓存的请求。如果与收到的数据包关联的条目在系统缓存中不存在,则系统缓存将确定是否设置了系统缓存的反压指示符。如果设置了背压指示器,则将接收到的数据包写入共享内存。如果未设置反压指示器,则系统高速缓存确定是否从系统高速缓存中逐出数据以存储接收到的数据包。如果系统高速缓存的逐出速率已达到阈值,则系统高速缓存将设置反压指示符,并将接收到的数据包写入共享内存。如果收回速度尚未达到阈值,则系统缓存确定可用条目,并将接收到的数据包写入系统缓存中的可用条目。

著录项

  • 公开/公告号US9152564B2

    专利类型

  • 公开/公告日2015-10-06

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号US201213687971

  • 发明设计人 DEEPAK MITAL;WILLIAM BURROUGHS;

    申请日2012-11-28

  • 分类号G06F7/38;G06F9/00;G06F9/44;G06F15/00;G06F12/08;H04L12/861;G06F15/78;H04L29/06;

  • 国家 US

  • 入库时间 2022-08-21 15:18:31

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