A SYSTEM FOR DEVELOPING MODEL OF TEST-ENVIRONMENT FOR HARDWARE DESCRIPTION LANGUAGE/S THAT DESIGNS AND MODELS ELECTRONICS CIRCUITS AND A METHOD THEREOF

摘要

A system for developing model of test-environment for hardware description language/s that designs and models electronics circuits, serves substantial enhancement in reduction of development time, flexibility and reduction of errors for developing models in digital circuit that has relevance in processing of designing and testing of model used for integrated circuit(s). The system works on network computers or similar electronics machines where one can use for development of the test bench in VHDL or Verilog HDL with the help of said invention. The GUI enables intuitive method to select the predefined definitions of virtual test patterns generator models which in turn reduce the human errors substantially.