HIERARCHICAL DIGITAL SYSTEMS MODELING UTILIZING HARDWARE DESCRIPTION LANGUAGES FOR COMPUTER ENGINEERING EDUCATION

摘要

This paper describes a hierarchical modeling approach and teaching methodology for digital microcomputer system modeling including abstract event modeling, mixed-mode event and timing-based, and gate level modeling. A structured instructional approach to fundamentals of computer design and simulation is given based on the Verilog hardware description language (HDL). Example models are given for common digital system components which illustrate the hierarchical learning model presented. Example simulation methods, various simulation hierarchies, and graphical simulation output are presented for the Verilog models discussed. Aspects of the simulation hierarchy are given with respect to system complexity, and simulation complexity for implementation and testing. Finally, educational aspects and merits, with emphasis on student perception and evaluation, of this language as a design tool are presented.