ABSTRACT OF THE INVENTION Network on chip is establishing itself as interconnect for high performance multi core systems. Currently the systems are realized using two dimensional topologies like mesh, torus etc. Research outcome in fabrication technology is reducing the feature size of silicon processes which enables more logic to be implanted on silicon. This was well complemented with improvement in packaging technology which led to vertical stacking of logic to form of three dimensional structures. This note introduces a new three dimensional topology - SMITH A: Scalable Modular Interconnect for Three dimensional High performance Applications. The note discusses the routing algorithm also.
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