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serial core architecture nonvolatile memory

机译:串行核心架构非易失性存储器

摘要

System memory (100) comprising: memory bank (104) for supplying read data flow serial bit in response to a read operation and to receive write data bit stream in series in response to an operation of writing; and serial data path (102) for connecting the read data bit stream and serial write data bit stream in series between the memory bank and an input / output (112); where the route serial data includes a mediator data (114) to receive access data serially from the input / output, where the access data including a command and an address, where the mediator data includes converter command data (124) to convert the command and address in a parallel format and switch path (126) for selectively connecting the input / output (112) to the drive command data (124) or the bank of memory (104) for reading data flow serial data portion from the memory bank (104) during the read operation.
机译:系统存储器(100)包括:存储器组(104),用于响应于读操作而提供读数据流串行位,并响应于写操作而串行接收写数据位流;以及串行数据路径(102),用于在存储体和输入/输出(112)之间串联连接读数据位流和串行写数据位流。其中路由串行数据包括介体数据(114)以从输入/输出串行接收访问数据,其中访问数据包括命令和地址,其中介体数据包括转换器命令数据(124)以转换命令,并行格式的地址和切换路径(126),用于有选择地将输入/输出(112)连接到驱动命令数据(124)或存储体(104),以从存储体(104)读取数据流串行数据部分)。

著录项

  • 公开/公告号ES2524613T3

    专利类型

  • 公开/公告日2014-12-10

    原文格式PDF

  • 申请/专利号ES20070845589T

  • 发明设计人 KIM JIN-KI;

    申请日2007-11-26

  • 分类号G11C5/02;G11C7/10;G11C7/12;G11C16/10;G11C16/16;G11C16/24;

  • 国家 ES

  • 入库时间 2022-08-21 15:12:06

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