CACHE COHERENT NOC WITH FLEXIBLE NUMBER OF CORES, I/O DEVICES, DIRECTORY STRUCTURE AND COHERENCY POINTS

摘要

The present application is directed to designing a NoC interconnect architecture by a means of specification, which can indicate implementation parameters of the NoC including, but not limited to, number of NoC agent interfaces, and number of cache coherency controllers. Flexible identification of NoC agent interfaces and cache coherency controllers allows for an arbitrary number of agents to be associated with the NoC upon configuring the NoC from the specification