ARM NI-700 PUTS A NOC IN CORELINK: DSU-110 Connects Arm v9 CPUs in a Cache-Coherent System

摘要

Although the Arm v9 "Matterhorn" CPUs introduce many features that boost performance and power efficiency in client devices, they're unable to deliver those gains without similar improvements in the interconnects that form the backbone of a multicore SoC. To support the new CPUs, Arm developed a new dynamic shared unit (DSU) and two new CoreLink interconnect products, including its first net-work-on-a-chip (NoC). All the new products are available for licensing. For cache-coherent operations within the CPU cluster, the second-generation DSU-110 completely revises the DynamIQ microarchitecture. Arm says it increases L3-cache-hit bandwidth by up to 5x relative to the previous design, and it can reduce CPU leakage power by up to 75% as well. The DSU supports the new Cortex-X2, Cortex-A710, and Cortex-A510 CPUs (see page 1, "Arm v9 Yields Three New CPUs").