MIPI D-PHY CIRCUIT FOR LOW-POWER MODE

摘要

The present invention relates to an MIPI D-PHY circuit operated in a low power (LP) mode. According to one embodiment of the present invention, provided is the MIPI D-PHY circuit operated in the low power mode which includes a low power transmitter which controls the change rate of a full swing output voltage in the maximum current amount range and a low power receiver which receives the full swing output voltage and generates a preset full swing logic output based on a first reference voltage and a second reference voltage. The MIPI D-PHY circuit operated in the low power mode according to one embodiment of the present invention processes an asynchronous command with a voltage swing of 1.2V and the maximum 10Mbps speed in an MIPI D-PHY analog block for a low power interface with high performance.