Design of D-PHY chip for mobile display interface supporting MIPI standard

摘要

This paper presents a MIPI (Mobile Industry Processor Interface) D-PHY (physical layer) analog part that meets the MIPI Alliance standard that supports high-speed (HS) transmitter (HS-TX) and receiver (HS-RX) modes as well as low-power (LP)-TX, LP-RX, and LP-contention detection (CD) modes. MIPI is a flexible, source synchronous serial interface standard connecting a host processor to display and camera modules on mobile devices. The standard supports signal levels of 1.2 Vpp at 10 Mbps in LP mode and 0.2 Vpp at 80-1000 Mbps in HS mode. In the design, we propose the use of special circuits: LP-TX controls the slew-rate and limits current with a push-pull driver that reduces electromagnetic interference, LP-RX maintains good noise immunity using a hysteresis comparator and a set/reset (SR) latch, HS-TX supports synchronous differential high-speed data transmission based on Scalable Low Voltage Signaling (SLVS), and HS-RX stably receives transferred data with DC variations and AC noise using a very-wide-common-mode range differential amplifier (VCDA). We implemented the MIPI D-PHY analog chip using 0.13 μm CMOS process under a 1.2 V supply. We found that the HS-RX block shows a jitter of less than 5% at 1 Gbps and a power consumption of 0.74 mW that is suitable for the standard.