首页> 外国专利> BOTTOM GATE BOTTOM CONTACT THIN FILM TRANSISTOR, METHOD OF MANUFACTURING BOTTOM GATE BOTTOM CONTACT THIN FILM TRANSISTOR, AND IMAGE DISPLAY DEVICE

BOTTOM GATE BOTTOM CONTACT THIN FILM TRANSISTOR, METHOD OF MANUFACTURING BOTTOM GATE BOTTOM CONTACT THIN FILM TRANSISTOR, AND IMAGE DISPLAY DEVICE

机译:底部门底部接触薄膜晶体管,制造底部门底部接触薄膜晶体管和图像显示装置

摘要

PROBLEM TO BE SOLVED: To provide a method of manufacturing a thin film transistor where a drain electrode is not covered by mistake, when covering the source wiring with a protective layer, and to provide a thin film transistor manufactured by that method, and an image display device.SOLUTION: In a bottom gate, bottom contact thin film transistor, a protective layer 8 for protecting a semiconductor layer is formed so as to cover the gate electrodes 2 formed on a substrate 1, i.e., a support, at regular intervals in stripe, stripe semiconductor layers 7 formed in parallel at regular intervals perpendicularly to the gate electrode, while connecting the source electrode 4 and drain electrode 5 formed on a gate insulator layer 3 covering the gate electrode and the substrate, and source wiring 6 connecting the semiconductor layer thereof and the source electrode and the source electrode arranged in parallel with the semiconductor layer thereof in parallel.SELECTED DRAWING: Figure 1
机译:解决的问题:提供一种在用保护层覆盖源极布线时没有错误地覆盖漏电极的薄膜晶体管的制造方法,以及通过该方法制造的薄膜晶体管和图像解决方案:在底栅,底接触薄膜晶体管中,形成用于保护半导体层的保护层8,以覆盖形成在基板1(即,支撑体)上的栅电极2,该栅电极2以规则间隔隔开。条纹状地,在连接形成于覆盖栅电极和基板的栅极绝缘体层3上的源电极4和漏电极5的同时,以与栅电极垂直的规则间隔平行地形成的条纹半导体层7和连接半导体的源极布线6层与源极和源极平行排列,并与半导体层平行。图1

著录项

  • 公开/公告号JP2016092059A

    专利类型

  • 公开/公告日2016-05-23

    原文格式PDF

  • 申请/专利权人 TOPPAN PRINTING CO LTD;

    申请/专利号JP20140221310

  • 发明设计人 MATSUBARA RYOHEI;CHUJO HINA;

    申请日2014-10-30

  • 分类号H01L21/336;H01L29/786;H01L51/05;G02F1/1368;H01L51/50;H05B33/14;G09F9/30;G09F9/00;

  • 国家 JP

  • 入库时间 2022-08-21 14:46:47

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