Solutions The bias circuit for the static ram (SRAM) which has ritein teiru akusesudo (RTA) mode. Memory is formed with the plural memory array blocks (26) which include the 8 T or 10 T type SRAM cell to which each has individual read-out and entry data pass. The bias device (27) is included inside each memory array block, (26) for example, the individual line and the association and relation one which is attached or is connected between the reference voltage node and the gland node of the invertor which it is crossed is connected inside each memory cell inside the plural lines. With normal operation mode, the switch transistor (29) which is connected to the bias device in parallel gland voltage biass the invertor which it is crossed is connected of each cell to on. With RTA mode, the switch transistor, the bias device rises the standard bias to the invertor which it is crossed is connected to an off, decreases the electricity consumption by the cell of this mode. Selective figure Figure 2
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