Static RAM type memory device i.e. portless static RAM memory device, has control unit delivering control signal to gate of transistor of additional cell to place memory-cells in read mode and additional cell in write mode, or conversely

摘要

The device has a memory plane (PM) comprising a column of static RAM memory cells (CEL). Supply voltage (Vdd) is supplied to bit lines (BLTP, BLFP). A control unit (MC1) sets controllable additional access units (PGT, PGN) in one of two states. Another control unit (MC2) delivers a control signal to a gate of a single access transistor of one of the memory cells of the column and another control signal to a gate of a single access transistor of an additional memory cell (CLS) in order to set the memory-cells in a read mode and the additional cell in a write mode, or conversely. The additional access unit is an N channel type metal-oxide-semiconductor transistor.