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Reference voltage generating circuit, D / the A conversion circuit, and a display panel driving semiconductor device using such a semiconductor device, and electronic apparatus

机译:基准电压产生电路,D / A转换电路以及使用该半导体装置的显示面板驱动半导体装置及电子设备

摘要

PROBLEM TO BE SOLVED: To provide a reference voltage generation circuit whose resistance value in latch-up resistance test is high and whose chip size can be easily reduced.;SOLUTION: In a reference voltage generation circuit having three or more reference voltage terminals, an N-type semiconductor region 15 is disposed so as to be held between an N-type semiconductor region 13a formed in a P-type well 11 constituting an ESD protection element connecting to one of a pair of adjacent reference voltage terminals and an N-type semiconductor region 13b formed in the same P-type well 11 constituting an ESD protection element connecting to the other of the pair of adjacent reference voltage terminals. An intermediate voltage higher than a substrate potential applied to the P-type well 11 and lower than a predetermined threshold voltage is applied to the N-type semiconductor region 15, whereby collector losses due to a collector current flowing in the N-type semiconductor region 13a or 13b caused by a parasitic transistor at the time of latch-up resistance test are reduced.;COPYRIGHT: (C)2013,JPO&INPIT
机译:要解决的问题:提供一种基准电压发生电路,该电路的闩锁电阻测试中的电阻值高并且可以轻松减小芯片尺寸。解决方案:在具有三个或更多基准电压端子的基准电压发生电路中, N型半导体区域15被布置为被保持在形成于P型阱11中的N型半导体区域13a之间,该N型半导体区域13a构成连接到一对相邻参考电压端子之一的ESD保护元件的N型半导体区域13a。在同一P型阱11中形成的半导体区域13b构成ESD保护元件,该ESD保护元件连接到一对相邻的参考电压端子中的另一个。将高于施加到P型阱11的衬底电势并且低于预定阈值电压的中间电压施加到N型半导体区域15,由此由于在N型半导体区域中流动的集电极电流而引起的集电极损耗。降低了闩锁电阻测试时由寄生晶体管引起的图13a或13b .;版权所有:(C)2013,JPO&INPIT

著录项

  • 公开/公告号JP5878784B2

    专利类型

  • 公开/公告日2016-03-08

    原文格式PDF

  • 申请/专利权人 シャープ株式会社;

    申请/专利号JP20120034233

  • 发明设计人 下村 奈良和;

    申请日2012-02-20

  • 分类号H01L21/822;H01L27/04;H03M1/76;

  • 国家 JP

  • 入库时间 2022-08-21 14:39:56

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