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Patterning method for IC fabrication using 2-D layout decomposition and synthesis techniques
Patterning method for IC fabrication using 2-D layout decomposition and synthesis techniques
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机译:利用二维布局分解和合成技术制造集成电路的图案化方法
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摘要
Various multiple-mask patterning methods by employing the layout decomposition and stitching technique are invented. The inventions pertain to methods of decomposing and synthesizing two-dimensional features on a substrate having the feature density increased to multiple times (up to eight times) of what is possible using the standard optical lithographic technique; and methods to release the overlay requirement when patterning the critical layers of semiconductor devices. The invented processes allow IC designers to pattern random two-dimensional circuit features that are beyond the resolution capability of optical lithography. They provide production-worthy methods for the semiconductor industry to continue IC scaling beyond the half pitch of 10 nm.
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