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CIRCUIT DIVISION METHOD FOR TEST PATTERN GENERATION AND CIRCUIT DIVISION DEVICE FOR TEST PATTERN GENERATION

机译:用于生成测试图案的电路划分方法以及用于生成测试图案的电路划分设备

摘要

A circuit division method for test pattern generation in which a computer performs processes of: acquiring, for each of a plurality of blocks included in a target circuit for test pattern generation, a first feature amount regarding a size of each block and a second feature amount regarding a function of the block; classifying the plurality of blocks into a plurality of groups so that blocks for which the acquired first feature amount is within a first predetermined range and the acquired second feature amount is within a second predetermined range belong to an identical group; and assigning, for each of the classified groups, each of the blocks included in the group to one of a plurality of divided circuits of a division number based on a ratio of the number of blocks included in the group to the division number by which the plurality of blocks are divided.
机译:一种用于测试图案生成的电路划分方法,其中计算机执行以下处理:对于用于测试图案生成的目标电路中包括的多个块中的每个,获取与每个块的大小有关的第一特征量和第二特征量关于模块的功能;将所述多个块划分为多个组,以使得所获取的第一特征量在第一预定范围内且所获取的第二特征量在第二预定范围内的块属于同一组;并且,基于所述组中包含的块数与所述划分数的比,将所述组中包括的每个块分配给所述划分数的多个划分电路之一。多个块被划分。

著录项

  • 公开/公告号US2016154056A1

    专利类型

  • 公开/公告日2016-06-02

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号US201514938000

  • 发明设计人 DAISUKE MARUYAMA;

    申请日2015-11-11

  • 分类号G01R31/3177;G01R31/317;

  • 国家 US

  • 入库时间 2022-08-21 14:34:56

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