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Power LDMOS semiconductor device with reduced on-resistance and manufacturing method thereof
Power LDMOS semiconductor device with reduced on-resistance and manufacturing method thereof
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机译:导通电阻降低的功率LDMOS半导体器件及其制造方法
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摘要
An electronic semiconductor device including a semiconductor body having a first structural region and a second structural region, which extends on the first structural region and houses a drain region; a body region, which extends into the second structural region; a source region, which extends into the body region; and a gate electrode, which extends over the semiconductor body for generating a conductive channel between the source region and the drain region. The device includes a first conductive trench extending through, and electrically insulated from, the second structural region on one side of the gate electrode; and a second conductive trench extending through the source region, the body region, and right through the second structural region on an opposite side of the gate electrode, electrically insulated from the second structural region and electrically coupled to the body region and to the source region.
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