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Fractional N-PLL circuit, oscillator, electronic device, and moving object

机译:小数N-PLL电路,振荡器,电子设备和移动物体

摘要

In order to appropriately set an operation range of a voltage controlled oscillator without excessively increasing a frequency at which delta-sigma modulation is performed, a fractional N-PLL circuit includes: a voltage controlled oscillator that is configured to set plural output frequency ranges; a frequency selection circuit that selects one output frequency range; a division circuit; and a division setting circuit that sets a division ratio of the division circuit. The division setting circuit performs, while the frequency selection circuit is searching for the plural output frequency ranges of the voltage controlled oscillator, the delta-sigma modulation at a frequency lower than a frequency after the frequency selection circuit terminates the search.
机译:为了在不过度增加执行Δ-∑调制的频率的情况下适当地设置压控振荡器的工作范围,分数N-PLL电路包括:压控振荡器,被配置为设置多个输出频率范围;以及频率选择电路,选择一个输出频率范围;分压电路;分频设置电路,其设置分频电路的分频比。在频率选择电路正在搜索压控振荡器的多个输出频率范围时,分频设置电路以低于频率选择电路终止搜索之后的频率的频率执行Δ-∑调制。

著录项

  • 公开/公告号US9490820B2

    专利类型

  • 公开/公告日2016-11-08

    原文格式PDF

  • 申请/专利权人 SEIKO EPSON CORPORATION;

    申请/专利号US201514848902

  • 发明设计人 NOBUTAKA SHIOZAKI;

    申请日2015-09-09

  • 分类号H03L7/06;H03L7/08;H03L7/093;H03L7/14;H03M3/00;

  • 国家 US

  • 入库时间 2022-08-21 14:30:33

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