The architecture of circuit and method for processing recursive data accessed memory latency without penalty

摘要

The architecture of circuit and method for processing recursive data accessed memory without penalty in latency, comprising a recursive processing module, multiplexer, the temporary registration and control module.Said processing module carries out the processing of each data read in the address X of gust of reading received.Generating the corresponding command to rewrite the data in the same address - x; said bank of register temporary replica storage of a small quantity of the most recent data that have been or are being stored in the memory and said control module determines if the data to be read by P Rocessamento should come by the barrage of reading from memory or whether it should be recovered from the Bank of registrThe place. Each given newly and simultaneously processed in memory and in a bank of registers location is treated so that the subsequent address of reading has been updated recently, the data will be recovered from the recording site, instead of being read out of the memory.