Low-power low-latency optical network architecture for memory access communication

摘要

The interconnection network plays a vital role in improving the performance of modern computing systems. Traditional electronic interconnect is subject to latency, power consumption, and bandwidth problems. A low-power low-latency optical network architecture is proposed in this paper to interconnect cores and memory. The proposed architecture is made up of optical subnetworks using seven wavelengths. The optical subnetwork is constructed by some switching blocks, which are able to provide the memory access communication from all cores to ranks at the same time. Compared with traditional electronic bus-based core-to-memory architecture, the simulation results based on the PARSEC benchmark show that the average latency decreases by 54.05%, and the average power consumption decreases by 86.25%. Due to the enhancement of parallel access, the total runtime of applications decreases by 66.43%.