首页> 外国专利> A METASTABILITY DETECTION AND CORRECTION CIRCUIT FOR SET RESET LATCH

A METASTABILITY DETECTION AND CORRECTION CIRCUIT FOR SET RESET LATCH

机译:SET RESET闩锁的转移检测和更正电路

摘要

The present invention relates to a metastability detection and correction circuit of an SR latch which detects and corrects metastability of SR latch decision in a successive approximation type analog digital converter structure using the SR latch which is a differential register. The metastability detection and correction circuit of the SR latch includes: an input part which receives a first output and a second output, an enable signal enabling the SR latch, and a clock informing the elapse of previously assigned comparison operation time of a comparator from the SR latch connected to a rear of the comparator of a successive approximation type analog digital converter; a latch output detection part which is enabled by the first output or the second output when the first output and the second output have an equal value; a comparator operation time detection part which is enabled in response to an edge trigger signal of the clock under the state that the enable signal is enabled; and an output part which outputs a flag signal under the state that the latch output detection part and the comparator operation time detection part are enabled.
机译:SR锁存器的亚稳性检测和校正电路技术领域本发明涉及一种SR锁存器的亚稳性检测和校正电路,该电路在使用作为差分寄存器的SR锁存器的逐次逼近型模拟数字转换器结构中,检测并校正SR锁存器判定的亚稳性。 SR锁存器的亚稳态检测和校正电路包括:输入部分,其接收第一输出和第二输出;使能信号,其使能SR锁存器;以及时钟,其从比较器通知先前分配的比较器的比较操作时间的经过。 SR锁存器连接到逐次逼近型模拟数字转换器的比较器的后部;锁存器输出检测部分,当第一输出和第二输出具有相等的值时,由第一输出或第二输出使能;比较器操作时间检测部分,在使能信号被使能的状态下响应于时钟的边沿触发信号而被使能;在锁存输出检测部和比较器动作时间检测部被使能的状态下,输出标志信号的输出部。

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