METHOD AND APPARATUS FOR CONVERT SPICE NETLIST TO FPGA SYNTHESIZABLE VERILOG CODE

摘要

Disclosed is a method and apparatus for converting a SPICE netlist into an FPGA-synthesizable Verilog code. The method for converting a SPICE netlist into an FPGA-synthesizable Verilog code, which is proposed by the present invention, includes: a first conversion step for converting a grammar code of a received SPICE netlist into a grammar code of a transistor-level Verilog, and selecting a wire to be used as an input and an output, using a graphic user interface; and a second conversion step for converting the grammar code of the transistor-level Verilog into an FPGA-synthesizable grammar code of a Verilog. The present invention can convert a SPICE netlist into a synthesizable Verilog code, and thus, can substitute simulation using a software manner for simulation using a hardware manner, thereby shortening a logic verification time.