An interconnect structure comprising metal backside redistribution lines with very small pitch combined with vias

摘要

A 3D interconnect structure and method of fabrication are described in which metal redistribution layers (RDLs) are integrated with silicon vias (TSVs) and using a "via resist" type process. A silicon nitride or silicon carbide passivation layer may be provided between the back side of the thinned device wafer and the RDLs to provide a hermetic barrier and polishing stop layer during the process.