7-transistor static random access memory bit cell with reduced read disturb

摘要

The system and method includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, a second pull-up transistor, a second pull-down transistor, and a second A 7-transistor static random access memory (7T SRAM) bit cell comprising a second inverter having a storage node. The second storage node is coupled to the gates of the first pull-up transistor and the first pull-down transistor. A transmission gate selectively couples the first storage node to the gates of the second pull-up transistor and the second pull-down transistor during the write operation, standby mode, and hold mode, and during the read operation, the first Are configured to be selectively disconnected from the gates of the second pull-up transistor and the second pull-down transistor. The 7T SRAM bit cell can be read or written to through the access transistor coupled to the first storage node.