FPSCR STICKY BIT HANDLING FOR OUT OF ORDER INSTRUCTION EXECUTION

摘要

A hardware execution unit within a processor core executes a second instruction, which is part of a software thread, and which is executed out of order within the software thread. A sticky bit flip detection hardware device detects a change to a sticky bit in a floating-point status and control register (FPSCR) within the processor core. An instruction issue hardware unit identifies a first instruction that is in the software thread that is capable of reading or clearing the sticky bit. A flushing execution unit flushes all results of instructions from an instruction completion table (ICT) that include and are after the first instruction in the software thread. A hardware dispatch device dispatches all instructions that include and are after the first instruction in the software thread for execution by one or more hardware execution units within the processor core in a next-to-complete (NTC) sequential order.