LDPC SHUFFLE DECODER WITH INITIALIZATION CIRCUIT COMPRISING ORDERED SET MEMORY

摘要

A low-density parity check (LDPC) decoding apparatus for performing shuffle decoding includes: an input wrapper, for receiving input data and padding the input data; an LDPC decoder, coupled to the input wrapper, for receiving the padded input data, performing a plurality of iterations of LDPC decoding upon the padded input data to generate channel values corresponding to the padded input data, and outputting a hard decision channel value in a final iteration; and an initialization circuit, coupled to the LDPC decoder, for receiving the input data in a first iteration of the plurality of iterations, storing the input data into an ordered set data, and immediately sending the ordered set data to the LDPC decoder.