Semiconducting memory has control signal generation circuit, set/reset circuit, column address decoder circuit, memory cell field, delay circuit that can alter/vary reset signal delay time

摘要

The memory device has a control signal generation circuit (2) for generating a set signal, a delay circuit (9), a set/reset circuit, a column address decoder circuit (5) and a memory cell field (6) for receiving the column address selection signal to perform a data transfer operation within a rise time duration of the signal. The delay circuit can alter or vary the delay time of the reset signal.